1. Technical Field
Embodiments disclosed herein relate to power management for integrated circuits and related systems. More particularly, some embodiments disclosed herein relate to systems and methods for sub-hierarchy clock control using hysteresis and threshold management.
2. Description of the Related Art
Advances in semiconductor processing and logic design have increased the amount of logic that is included on integrated circuit devices. These increases have resulted in computer systems evolving from multiple integrated circuits in a system to, for example, complete systems on individual integrated circuits. As the density of integrated circuits has grown, the power requirements for computing systems have also increased. As a result, there is a need for energy efficiency and energy conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, ultrabooks, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent.
As processor technology has advanced and the demand for performance has increased, the number and capacity of cache memories has followed. Some processors may have single level of cache memory and others may have multiple levels of caches. Some cache memories may be used for storing data, instructions, or both. Cache memories for storing other types of information are also used in some processors.
Cache memories may be defined by levels, based on their proximity to execution units of a processor core. For example, a level one (L1) cache may be the closest cache to the execution unit(s), a level two (L2) cache may be the second closest to the execution unit(s), and a level three (L3) cache may be the third closest to the execution unit(s), etc. When accessing information for an instruction to be executed, an execution unit may first query the level one cache. If the information is not stored in the level one cache (i.e., a cache miss), the level two cache may be queried, and so forth. If the information is not stored in any cache, the information may be accessed from other storage such as main memory or from disk storage. Since the latency associated with memory and disk storage accesses is much greater than the latency associated with cache accesses, cache memories have become larger to accommodate more data and/or instructions. However, these larger cache memories may consume more power than their smaller counterparts. As such, some processors may remove power to part or all of a cache memory when the processor is idle.